1. Field of the Invention
The present invention relates to a microcontroller that has a debug support unit (hereinafter referred to as a DSU), and more particularly to a microcontroller that has a DSU, which is capable of performing an instruction fetch operation and data access at high-speed with respect to an in-circuit emulator (ICE) which stores a program and data for debugging and whose function is to monitor the state of the CPU at the time of execution of program instruction code.
2. Description of the Related Art
Microcontrollers, which are implemented in controlled devices, such as, computer peripherals and consumer electronics, are connected via an external bus to an external memory in which a control program and data, and the like, are recorded, read out instruction code from this memory by outputting an instruction fetch request, and read or write predetermined data by outputting a data access request.
With a microcontroller of this kind, in a debug process at a development stage, the microcomputer is connected to an in-circuit emulator (ICE), which stores a control program, and data, and the like, and whose functions include monitoring states within the microcontroller at the time of execution of instruction code, and is caused to operate in an emulator mode. In order to be capable of operating in this emulator mode, a debug support unit (DSU) is installed, inside the microcontroller of a development stage, which controls access to the ICE.
The microcontroller contains, in addition to a CPU, a bus controller for accessing an external bus. Further, the CPU and bus controller are connected by an address bus and data bus, with a multiple bit structure, or the like, and both are capable of sending and receiving addresses and data, and the like, in parallel, during an access operation. This bus architecture is typically a simple structure in which an address and an access request are output from the CPU when a wait signal from the bus controller is canceled, and, upon receiving this access request, the bus controller converts this wait signal to a wait state and performs external access, and, upon obtaining the accessed data and instruction code shortly afterwards, the bus controller sends this data and instruction code to the CPU, and thus cancels the wait signal.
In a microcontroller of this kind, in order to implement debugging in the above-mentioned emulator mode, the address bus and data bus, or the like, are also connected to a DSU, and control of access between the DSU and the external ICE is required. In other words, the DSU obtains an access request from the CPU, converts a wait signal to a wait state, and outputs an access request to the ICE, and, if data and instruction code are obtained from the ICE, sends this data and instruction code to the CPU and cancels the wait signal.
However, the external ICE, in addition to storing programs and data, or the like, has the function of monitoring the internal state of the microcontroller. A great number of signal lines are employed to monitor this internal state, therefore such a large number of signal lines occupy the majority of the external pins of the microcontroller. As a result, the number of external pins that can be utilized with the tool bus for the transfer of data and addresses, and the like, between the DSU and ICE is limited, and this tool bus cannot implement a large number of multiple-bit structures like the data bus inside the microcontroller, which may utilize a greater number of bits. Consequently, addresses and data must be transferred by serial transfer, and by using time-sharing, via a tool bus, which is between the DSU and ICE, that has a structure of a low number of bits.
For example, unlike the address bus and data bus inside the microcontroller, which are of a 16-bit or 32-bit structure and which perform parallel transfer of addresses and data in a single cycle, the tool bus between the DSU and ICE is of a 4-bit structure. The DSU therefore performs parallel to serial conversion of the addresses and data received from the CPU and performs serial transfer to the ICE by using time-sharing. Thereafter, the DSU performs serial to parallel conversion of the instruction code received from the ICE and sends this converted code to the CPU. The DSU waits until this series of instruction fetch operations is complete before sending a wait signal to the CPU.
Such limitations on data transfer give rise to a problem in that, during operation in the emulator mode, when an instruction fetch operation is frequently generated, the tool bus fills up considerably only by receiving instruction code, which in turn leads to a poor debug processing capacity.